The invention relates generally to the field of information storage, more specifically to hard disk drives and in particular to preamplifier circuits.
U.S. Pat. No. 5,831,888 entitled xe2x80x9cAutomatic Gain Control Circuitxe2x80x9d and assigned to Texas Instruments Incorporated, the assignee of the present invention, sets forth generally the description of disk storage. Hard disk drives (HDD) are one type of disk storage that are particularly used in personal computers today. The HDD device generally includes a magnetic storage media, such as rotating disks or platters, a spindle motor, read/write heads, an actuator, a preamplifier, a read channel, a write channel, a servocontroller, a memory and control circuitry to control the operation of the HDD and to properly interface the HDD to a host or system bus. The following U.S. Patents describe various aspects of HDD devices:
Prior art FIG. 1 illustrates a disk/head assembly 12 and a preamplifier 14. The preamplifier 14 handles both read functions and write functions. Not illustrated in FIG. 1, for clarity, is the Magentoresistive (MR) head. The unshown MR head works through magnetic media and it has both functions, read and write, with a different portion of the head performing each function. The write function portion of the MR head is inductive and the read function portion of the head acts as a magnetic resistive element. A write occurs through an inductive element to the magnetic media disk assembly 12 and a read occurs by sensing the magnetic shifts in the disk assembly 12 by using the resistive read element. The preamplifier 14 connects to the unshown MR head.
The preamplifier 14 typically is a multistage preamplifier having an initial amplification stage, a middle amplification stage and a final amplification stage. The initial amplification stage is usually of the single ended variety as opposed to the middle amplification stage which is usually of the differential variety. The single ended variety is particularly advantageous in hard disk drive applications as one input to the preamplifier is the MR head input and the other input is ground. Effectively, therefore, it has only one input, the MR head input, and so it is referred to as single ended. Two types of single ended initial amplification stages exists: current bias current sense design systems; and, voltage sense design systems.
FIG. 2 illustrates a prior art current bias current sense preamplifier such as suitable for preamplifier 14 of prior art FIG. 1. Current bias means that the preamplifier sends a constant current through the MR head. Current sense means that when the MR head moves over data stored on the disk/head assembly 12, the input signal to the MR head is a current signal. The input signal is thus indicative of a current change in the head. (In a voltage sense preamplifier, the input signal is a voltage signal as opposed to a current signal.) In FIG. 2, Rhead is a resistor that represents is the MR head. Lhead is a wire that goes from the preamplifier to the MR head and is represented as an inductor. The triangular figure represents the preamplifier. One input to the preamplifier is the MR head input and the other input to the preamplifier is ground. Since it is a current sense preamplifier, by definition it has a very low input impedance (which in this case, is about 5 ohms).
Prior art FIG. 3 illustrates a portion of the read channel of the current bias current sense preamplifier 14 of FIG. 2. The resistive portion of the MR head is represented by the resistor Rmr. Rmr0 represents head 0 and Rmr1 represents head 1. In typical mass storage devices of the HDD type, the preamplifier 14 may have as many as 1 to 8 channels. An initial amplification stage 18 of preamplifier 14 connects to the resistive portion Rmr of the MR head. Later gain stages 20 of preamplifier 14 are connected to the outputs of initial amplification stage 18 at nodes P and Q. The read path outputs flow from the later gain stages 20. Amplifier Rma is the read channel middle amplifier and amplifier Roa is the read channel output amplifier. Both amplifiers are of the differential type. The head selection is performed on preamplifier 14 from an unillustrated head select logic stage. Transistor M2 represents the read channel input enabling MOS transistor for head 0.
In FIG. 3, the architecture of initial amplification stage 18 of preamplifier 14 is constructed as that of a single ended amplifier as opposed to a differential amplifier. On the RL load side of the single ended amplifier, the bias current Ib travels through the load resistor RL and through the collector of transistor Q1 to set the voltage on node M. On the constant voltage side of the single ended amplifier, the bias current Ib/k (k is a scaling constant) travels through the scaling reference resistor Ref to set the voltage on node N. In hard disk drives, during a read operation, the current in the read head (represented by Imr) is biased up to a certain level, which is typically around 2xe2x80x948 mA. This bias current Imr is established through a feedback loop created by transconductance amplifier 22 across nodes M and N whose output is connected to the base of the input transistor Q0 through MOS switch M2. This, in essence, creates a pseudo-balanced output on the reader load resistors such as would exist if a differential amplifier were used in the initial amplification stage 18 as dc nodes M and N will be at the same potential. Since the head resistance Rmr0 is connected to transistor Q0, the impedance looking from Rmr into transistor Q0 is very small because it is looking into the emitter of the bipolar transistor Q0. (Emitter impedance is low for bipolar transistors - - - only a few ohms.) A problem, however, with low impedance is bandwidth rolloff as will be explained later below.
In operation of prior art FIG. 3, when head 0 is selected by unillustrated head select logic circuitry (which establishes a current Imr on the gate of MOS transistor M2) NPN bipolar transistors Q0 and Q1 are on. Together with the load resistor RL, they form a cascode amplifier. A cascode amplifier is a high bandwidth amplifier. The transistor Q0 is a common base amplifier and the transistor Q1 acts as a common base amplifier. As the magnetic resistive head moves over data, the head resistance Rmr varies. This can be modeled by an alternating current ac signal in series with the Rmr resistor. The transistors Q0 and Q1 amplify this signal. The ac signal goes to the load resistor RL and produces an ac signal at node M which is the input of latter gain stage 20 that is a differential amplifier. The other input of the amplifier 20 is node N that should be at a dc bias voltage equal to the voltage on the load resistor RL node M. The node N, which is the constant voltage side of the later gain stage amplifier 20, should not have an alternating current signal on it. The transconductance amplifier 22 and the capacitor C1 form a feedback loop with the cascode amplifier Q0 and Q1. The purpose of the loop is to make sure that node M dc voltage on the signal side of the load resistor RL is the same as the dc voltage on node N. If the dc voltage on node M and node N are the same, the input voltages on differential amplifier 20 are the same. On node N, there is no ac signal; on node M there is an ac signal. If the dc voltages are equal, then the differential later gain stage amplifier 20 will amplify the ac signal and send it to further gain stages.
FIG. 2a is a gain bandwidth plot for the signal at the input of the current bias current sense preamplifier 14 of FIGS. 2 and 3. At low frequencies, all the source frequencies, Vs, that go through the MR head appear on the preamplifier, Vin. As the frequencies increase, the head connection wire has an inductance Lhead that poses a large impedance. The frequency response thus mimicks a low pass filter and the 3 db corner frequency is effectively given by Rhead/Lhead.
For MR heads that have large inductances, or, for MR heads that have small resistances, the frequency response of the current bias current sense preamplifier is poor due to the lower 3 db corner frequency. This presents a problem because a recent trend in design is to have a large inductance for the wire trace going out to the MR head. Trace suspension assembly is one such favored technique employing large inductance. Further, the resistance in the MR head is decreasing. These lower levels effectively move the 3 db corner frequency of FIG. 2a in. So, while a current bias current sense preamplifier may have a very high bandwidth, if the input signal itself gets rolled off, the system bandwidth becomes low. Thus, for a high data rate disk drive system, not very much signal may be output from the current bias current sense preamplifier design.
One way to get rid of this frequency rolloff limitation is to make the input impedance Rin of the preamplifier very high. However, by default (because of the nature of the emitter impedance), a current bias current sense preamplifier cannot have very large impedance. If a high input impedance is required, the solution is to use a voltage sense preamplifier design. FIG. 4 depicts a voltage sense preamplifier and FIG. 4a is a gain bandwidth frequency plot for an ideal voltage sense preamplifier. When a very high input impedance exists, all of the signal that is on the MR head appears on the preamplifier regardless of the frequency. As such, the signal into the preamplifier does not decrease with frequency. Also, bandwidth does not depend on the resistance of the MR head. Thus, a voltage sense preamplifier appears to provide a good solution. How to accomplish it is, however, quite another matter because, in reality, the high input impedance of the voltage bias voltage sense preamplifier tends to be of a capacitive nature. As such, in FIG. 4, a capacitor is illustrated in the preamplifier instead of a resistor. This capacitance, together with the inductance Lhead in the assembly wire, unfortunately tends to introduce a peak in the frequency response as illustrated in FIG. 4b. This peak arises because of the resonance between Lhead and Cin. Peaking presents a problem of group delay to the read channel.
It is accordingly an object of the invention to provide a preamplifier having a high impedance without the peaking commonly associated with voltage sense preamplifiers.
Other objects and advantages of the invention will be apparent to those of ordinary skill in the art having the benefit of the description herein.
An inventive current bias voltage sense single ended preamplifier incorporates a PMOS transistor between the MR head and the input bipolar transistor to increase impedance on the input and increase bandwidth. A MR biasing circuit may be provided to provide a bias current for the MR head. The PMOS transistor and the input bipolar transistor sense a change in voltage signal on the MR head. An input capacitance cancellation circuit, whose amount of cancellation is variable, may be added to reduce the input capacitance and thereby control peaking.